1. Field of the Invention
This invention relates to design automation systems and methods and particularly to an enhanced method for preparing data for processing semiconductors, and more particularly, to the processing of complementary metal oxide semiconductor (CMOS) devices.
2. Description of the Prior Art
Since the advent of large scale integrated circuits (LSI), it has become possible to fabricate many thousands of circuits on a single semiconductor wafer chip. Proportional to the number of LSI circuits that may be fabricated on a single semiconductor chip is the complexity of the procedure for arranging such circuits for proper interconnection and isolation. This complexity has necessitated the creation of computer aided automatic design systems.
Typical of prior art directed to automatic circuit design systems are U.S. Pat. No. 3,475,621 issued Oct. 28, 1969 to A. Weinberger, U.S. Pat. No. 3,567,914 issued Mar. 2, 1971 to J. L. Neese, et al, and Defensive Publication No. T940,020 published Nov. 4, 1975 by G. E. Brechling, et al. These prior art systems typically disclosed techniques for devising orthogonal coordinates and using these coordinates to provide interconnect points for logical elements in the circuits to be fabricated. The techniques are sometimes referred to as cellular logic design and the logic elements are referred to as "cells." Data describing the logic elements, the orthogonal coordinates, and the interconnect points for the logical elements are input to a data processing unit and a circuit generation program operates the data processing unit to provide interconnection between the circuit elements or cells. However, these prior art systems are limited in the complexity of the circuits that can be fabricated using them because each requires a specification of all possible logic cells used with all possible interconnect points between the cells to enable fabrication of the logic function in a single pass. For example, a two-input NAND gate has 12 possible input and output wiring pattern combinations allowing only for vertical and horizontal wiring with fixed input and output locations. With the prior art systems, data describing each of these possible NAND gate configurations as a complete entity must be stored in the system. Each configuration is considered a cell. In addition to the input and output wiring configurations, multiple power levels could be needed for the technology. If two power options were available, the number of cells required increases to 24. The NAND gate may be used in combination with other basic logic cells, for example, OR, AND, NOR, and NOT. Each of these circuits requires a separate configuration, adding to the multiplicity of cells. This limits prior art techniques to relatively simple construction or to very specific implementation of more complex structures, for example, the high density logic array disclosed in U.S. Pat. No. 3,987,287 issued Oct. 19, 1976 to Cox et al. Furthermore, using the prior art techniques produces a circuit pattern that is not conducive to modification. Any change in any of the cells in the circuit requires a totally new circuit to be produced.
U.S. Pat. No. 4,377,849 to Finger et al, which is assigned to the assignee of the present invention seems to simply provide a way in which a layout can be developed hierarchically by allowing the description of basic cells which can then be assembled to form a larger macro. The cells are designed by hand rather than being generated automatically. Their cells are basic physical units which can be laid out on some rather small grid. There is no generation of the layout from the Boolean equation or some functional description of the circuit. Even in the single PLA example which is described, it appears as though the minimal functional form of the PLA itself is accomplished outside their package.
Other U.S. patents of general interest for their respective disclosures of integrated circuit structures are numbers 4,212,026; 4,218,693; 4,233,526; 4,402,044; and 4,412,240.
None of the methods described above can be utilized for the generation of static CMOS book layouts. According to the present invention, the layout of the functional circuits is generated from a Boolean equation. A computer program generates the layout of CMOS books from a high level functional description of the book. Such a program is useful in two respects. First, it may be used to design a book set in a minimal amount of time. Second, it may be used as a part of a synthesis system where the front end maps the logic into a set of series-parallel networks, with the program generating the layout of each such network. The input to the program is a description of the logic of the network in terms of AND and OR functions with an inverter at the output.